| Designer | Originally Damjan Lampret, now the OpenRISC Community (Stafford Horne etc.) |
|---|---|
| Bits | 32-bit, 64-bit |
| Introduced | 2000 |
| Version | 1.4[1] |
| Design | RISC |
| Encoding | Fixed |
| Endianness | Big; unimplemented stub for Little |
| Page size | 8 KiB |
| Extensions | ORFPX32/64,[2] ORVDX64[3] |
| Open | Yes (LGPL / GPL), hence royalty free |
| Registers | |
| General-purpose | 16 or 32 |
| Floating-point | Optional |
OpenRISC is a project to develop a series of open-source hardware based central processing units (CPUs) on established reduced instruction set computer (RISC) principles. It includes an instruction set architecture (ISA) using an open-source license. It is the original flagship project of the OpenCores community.
The first (and as of 2019[update] only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of 32-bit and 64-bit processors with optional floating-point arithmetic and vector processing support.[4] The OpenRISC 1200 implementation of this specification was designed by Damjan Lampret in 2000, written in the Verilog hardware description language (HDL).[5] The later mor1kx implementation, which has some advantages compared to the OR 1200,[6] was designed by Julius Baxter and is also written in Verilog. Software simulators also exist[7] which implement the OR1k specification.
The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL).
A reference system on a chip (SoC) implementation based on the OpenRISC 1200 was developed, named the OpenRISC Reference Platform System-on-Chip (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on field-programmable gate arrays (FPGAs),[8][9] and there have been several commercial derivatives produced.
Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.[10]
Instruction set
The instruction set is a reasonably simple traditional RISC architecture reminiscent of MIPS using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.
Another notable feature is a rich set of single instruction, multiple data (SIMD) instructions intended for digital signal processing.
Implementations
Most implementations are on field-programmable gate arrays (FPGAs) which give the possibility to iterate on the design at the cost of performance.
By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a crowdfunding project to build a cost-efficient application-specific integrated circuit (ASIC) to get improved performance. ORSoC faced criticism for this from the community.[citation needed] The project did not reach the goal.
As of May 2024[update], no open-source ASIC had been produced.
Commercial implementations
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which can run both the OpenRISC 1000 and BA12. Flextronics (Flex) and Jennic Limited manufactured the OpenRISC as part of an application-specific integrated circuit (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series).[11] Allwinner Technology use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.[12]
Cadence Design Systems have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera).[13]
TechEdSat, the first NASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.[14][15][16]
Academic and non-commercial use
Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz[17] and his team at the Institute for Integrated Systems at the Technical University of Munich have used OpenRISC in research into multi-core processor architectures.[18] The Open Source Hardware User Group (OSHUG) in the UK has on two occasions[19][20] run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,[21] which attracted the interest of Electronic Engineering Times (EE Times).[22] Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in JavaScript, running Linux with X Window System and Wayland support.[23]
Toolchain support
The OpenRISC community have ported the GNU toolchain to OpenRISC to support development in the programming languages C and C++. Using this toolchain the newlib, uClibc, musl (as of release 1.1.4), and glibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical integrated development environment (IDE) based on this toolchain. A project to port LLVM to the OpenRISC 1000 architecture began in early 2012.[24]
GCC 9 released with OpenRISC support.[25]
The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is a register-transfer level (RTL) model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see OVPsim), set up by Imperas.
Operating system support
Linux support
The mainline Linux kernel gained support for OpenRISC in version 3.1.[26] The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).[27] Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.
RTOS support
Several real-time operating systems (RTOS) have been ported to OpenRISC, including NuttX, RTEMS, FreeRTOS, eCos, and Zephyr.
QEMU support
Since version 1.2, QEMU supports emulating OpenRISC platforms.[28]
See also
- Amber (processor core) – ARM-Compatible OpenCores Project
- Free and Open Source Silicon Foundation
- J Core – SuperH-Compatible OpenCores Project
- OpenRISC 1200
- OVPsim, Open Virtual Platforms
- OpenSPARC – SPARC-Compatible OpenCores Project
- LEON
- LatticeMico32
- RISC-V
References
- ↑ "Published versions". Retrieved 2021-03-28.
- ↑ "Floating point extensions operating on 32-bit/64-bit". Retrieved 2021-03-28.
- ↑ "Vector/DSP extensions (SIMD) operating on 8-, 16-, 32- and 64-bit data". Retrieved 2021-03-28.
- ↑ "Architecture - OpenRISC". OpenRisc.io. Retrieved 2021-04-17.
- ↑ Clarke, Peter (2000-02-28). "Free 32-bit processor core hits the Net". Electronic Engineering Times (EE Times). San Francisco, California, United States: AspenCore Media. Retrieved 2019-03-21.
- ↑ "Implementations - OpenRISC". OpenRisc.io. Retrieved 2021-04-17.
- ↑ "Implementations - OpenRISC". OpenRisc.io. Retrieved 2021-04-17.
- ↑ Pelgrims, Patrick; Tierens, Tom; Driessens, Dries (2004). "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGAs" (PDF). De Nayer Instituut. 1.0. Archived from the original (PDF) on 2006-11-27. Retrieved 2009-03-03.
- ↑ Li, Xiang; Zuo, Lin. Open source embedded platform based on OpenRISC and DE2-70 (Masters). KTH Royal Institute of Technology (KTH), Sweden. Archived from the original on 2011-10-06., SoC program
- ↑ "System-on-Chip - OpenRISC". OpenRisc.io. Retrieved 2021-04-17.
- ↑ Samsung Open Source Release Center, follow the links → TV & VIDEO → TV → DTV → ETC → OR1200.zip
- ↑ Linux-sunxi project community wiki page on the AR100 controller. Retrieved on 20 July 2013.
- ↑ UVM Reference Flow Archived 2011-11-26 at the Wayback Machine, Accellera website (undated).
- ↑ Post to the openrisc mailing lists at lists.openrisc.net on 8 April 2012 by Fredrick Bruhn, CEO of ÅAC Microtec
- ↑ "Swedish breakthrough in space on NASA satellite with electronics from ÅAC Microtec". ÅAC Microtec (Press release). 2012-10-11. Archived from the original on 2014-01-18. Retrieved 2018-03-17.
- ↑ "Svenskt genombrott i rymden på NASA-satellit med elektronik från ÅAC Microtec" [Swedish breakthrough in space on NASA satellite with electronics from ÅAC Microtec] (Press release) (in Swedish). 2012-10-11. Retrieved 2018-03-16 – via Mynewsdesk.[dead link] Alt URL
- ↑ "Dipl.-Ing. Dipl.-Wirt.-Ing. Stefan Wallentowitz". 2009–2013. Archived from the original on 2013-04-13.
- ↑ Wallentowitz, Stefan; Wild, Thomas; Herkersdorf, Andreas. "Multicore Architecture and Programming Model Co-Optimization (MAPCO)" (PDF) (Research poster at the Sixth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), 11-17 July 2010). Terrassa (Barcelona), Spain. Archived from the original (PDF) on 10 February 2013. Retrieved 2018-10-29.
- ↑ Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000). OSHUG meeting #9, Skills Matter, 116-120 Goswell Road, London, 21 April 2011.
- ↑ Practical System-on-Chip (Program your own open source FPGA SoC). OSHUG meeting #17, Centre for Creative Collaboration, 16 Acton Street, London, 29 March 2012.
- ↑ OpenRISC 1200 soft processor Archived 2012-05-13 at the Wayback Machine. Blog post by Sven-Åke Andersson, 2 March 2012.
- ↑ Maxfield, Clive (2012-05-03). "Comparing four 32-bit soft processor cores". Electronic Engineering Times (EE Times). San Francisco, California, United States: AspenCore Media. Retrieved 2019-03-21.
- ↑ OpenRISC Emulator in JavaScript Can Run Wayland
- ↑ "llvm-or1k". GitHub. 2018-04-06. Retrieved 2019-03-21.
- ↑ "GCC 9 changelog". GNU. Retrieved 15 June 2022.
- ↑ "git.kernel.org - linux/kernel/git/torvalds/linux-2.6.git/tree - arch/openrisc/". git.kernel.org. Retrieved 2011-10-17.
{{cite web}}: CS1 maint: deprecated archival service (link) - ↑ "Linux 3.1". Kernel Newbies. Retrieved 2011-10-17.
- ↑ QEMU Changelog 1.2
External links
- Official website
- Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011) Article analyzing the law, technology and business of open source semiconductor cores
- Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
- Dynalith Systems company website.
- Imperas company website.
- Flex company website
- Jennic company website
- Eetimes article
- OpenRISC tutorial
- jor1k on GitHub, OpenRISC 1000 emulator in JavaScript